The present invention relates to a silicon substrate for a package and more particularly to a silicon substrate for a package having a cavity for accommodating a chip for an electronic device.
To advance the miniaturization and the reduced thickness of various kinds of electronic devices using a semiconductor device, a semiconductor package used for the semiconductor device needs to meet the miniaturization and the reduced thickness. Especially, to reduce the thickness, a silicon substrate for a package having a cavity is used (for instance, Patent Document 1). Namely, in the cavities dug from the surface of the substrate by etching, chips of the electronic devices such as a laser diode (LD), a photodiode (PD), a light emitting diode (LED), a micro-electro mechanical system (MEMS) or the like are mounted to absorb a part or all of the height of the chips of the electronic devices and reduce the thickness of the package. Thus, the package whose thickness is reduced in accordance with a specification requested by a client can be provided by using an ordinarily marketed silicon wafer whose selection of the thickness is limited to a range of a standard.
As shown in FIG. 1(1), a through electrode 14 formed by filling a through hole 12 that passes through a silicon substrate 10 in the direction of a thickness with a plating functions as a lead-out line to an external part from a terminal of an electronic device chip 18 mounted in a cavity 16. A thin film wiring 20 formed on a bottom surface 16B of the cavity by sputtering or a deposition that includes connection parts J1 and J2 to the through electrode 14 is patterned. In an external exposed end of the through electrode 14, a back wiring 21 including a pad for mounting the package on a mother board is formed.
As shown in FIGS. 1(2) and 1(3), end parts T1 and T2 of the through electrode 14 formed in the cavity 16 by plating is recessed into the through hole 12 (T1) or, on the contrary, protrudes from the bottom surface 16B of the cavity (T2) within an allowable range of a forming process. However, since a flattening process by polishing cannot be not applied to the bottom surface 16B of the cavity, the thin film wiring 20 needs to be formed on the end parts T1 and T2 of the through electrode under a state that the irregularities of the end parts T1 and T2 of the through electrode are left.
As shown in FIG. 1(2), in the case of the connection part J1 under a state that the end part T1 of the through electrode is recessed into the through hole 12 from the bottom surface 16B of the cavity, since an accumulation is little formed by sputtering or the deposition in a corner part K1 formed by the end part T1 and the side wall of the through hole 12, the thickness of the thin film wiring 20 is small, so that a disconnection is liable to arise.
Further, as shown in FIG. 1(3), in the case of the connection part J2 under a state that the end part T2 of the through electrode protrudes from the bottom surface 16B of the cavity, a distortion due to a differential thermal expansion between a material of the through electrode and the silicon substrate is concentrated on a part K2 in which the end part T2 protrudes in the form of a shade in the peripheral edge of the opening of the through hole 12, so that a disconnection is liable to arise.
As described above, a problem usually arises that in the connection parts J1 and J2 of the through electrode 14 and the thin film wiring 20 in the bottom surface 16B of the cavity, the disconnection is liable to occur.
[Patent Document 1] JP-A-2007-208041
It is an object to provide a silicon substrate for a package that prevents a disconnection between a through electrode and a thin film wiring in the bottom surface of a cavity from arising.
In order to achieve the above-described object, according to a first aspect, there is provided a silicon substrate for a package including:
a through electrode which fills a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate;
an end part of the through electrode in a bottom surface side of the cavity having a connection part to a wiring that forms an electric circuit including the chip of the electronic device; and
(1) a thin film wiring as the wiring, wherein the connection part is reinforced by a conductor connected to the thin film wiring.
According to a second aspect of the invention, there is provided the silicon substrate for a package according to the first aspect, wherein
the end part of the through electrode in the bottom surface side of the cavity is located at a position lower than the bottom surface of the cavity, and
a metal bump which fills a space in the through hole to the end part from the bottom surface of the cavity and is connected to the thin film wiring or a solder re-flow part forms the conductor.
According to a third aspect of the invention, there is provided the silicon substrate for a package according to the first aspect, wherein
the conductor is formed by a thick film wiring connected to the end part of the through electrode in the bottom surface side of the cavity and the thin film wiring in the periphery thereof.
According to a forth aspect of the invention, there is provided a silicon substrate for a package including:
a through electrode which fills a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate;
an end part of the through electrode in a bottom surface side of the cavity having a connection part to a wiring that forms an electric circuit including the chip of the electronic device; and
(2) a wire bonding part as the wiring, wherein the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.
According to a fifth aspect of the invention, there is provided the silicon substrate for a package according to the forth aspect, wherein
the end part of the through electrode in the bottom surface side of the cavity is located at a position lower than the bottom surface of the cavity, and
the connection part is formed by a first bonding part which fills a space in the upper part of the end part in the through hole and is connected to the end part.
According to a sixth aspect of the invention, there is provided the silicon substrate for a package according to the forth aspect, wherein
the end part of the through electrode in the bottom surface side of the cavity is located at a position lower than the bottom surface of the cavity, and
the connection part is formed by a second bonding part connected to the upper end of a metal bump which fills a space in the upper part of the end part in the through hole.
According to a seventh aspect, there is provided the silicon substrate for a package according to the forth aspect, wherein
the end part of the through electrode in the bottom surface side of the cavity is located at a position higher than the bottom surface of the cavity, and
the connection part is formed by a second bonding part connected to the end part.
In the present invention, the connection part is reinforced by the conductor connected to the thin film wiring and/or (2) the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity. Thus, a disconnection in the connection part can be prevented.